Method and circuit to investigate charge transfer array transistor characteristics and aging under realistic stress and its implementation to dram mosfet array transistor

ABSTRACT

An on-chip circuit and testing method to quantify a transistor charge transfer performance and charge retention capability of a DRAM cell in a realistic operational environment is described. The method and circuit can be extended to evaluate aging of the cell transfer device due to MOSFET wearout mechanisms that become activate during the charge transfer as well as during storage under operating or burn-in conditions. The on-chip circuit forces and senses a voltage to an individual DRAM storage capacitor, allowing the pulse test methodology characterize the individual storage capacitor charge leakage rate and quantify the rate of charge transfer between the bitline and the storage capacitor in the DRAM cell.

BACKGROUND OF THE INVENTION

[0001] 1. Technical Field of the Invention

[0002] This invention pertains to random access memory cells. In particular, this invention pertains to testing the performance characteristics of individual memory cells, thereby providing specific performance data typically unavailable in mass integration testing schemes.

[0003] 2. Description of the Prior Art

[0004] The building block of today's high-density DRAM chips is one provided with a single transistor cell. FIG. 1A shows the design of a conventional DRAM cell that uses a trench as Node Capacitor (NC) and a vertical NMOSFET, as the transfer device. In this design, XA and Buried Strap (BS) junctions and the vertical gate oxide formed along the top trench make up the vertical transfer device. The gate oxide is controlled by Word Line (WL), while Bit Line (BL) is used to transfer charge to NC. The charge transfer between Bit Line (BL) and NC occurs by inverting the channel of the transfer device (WL high) and adequately biasing BL (V(BL)>0). In this case, a logic 1 is stored in NC by transferring electrons from NC to BL, while a 0 is stored by transferring electrons from BL to NC. The 1 or 0 status is maintained in the storage capacitor by accumulating the channel (WL low). The DRAM cell is isolated by conveniently biasing PWELL (PW) and buried plate (BP). FIG. 1B illustrates a circuit schematic of the DRAM cell shown in FIG. 1A. A key feature of this structure is that the BS junction is directly connected to NC and is not directly addressable.

[0005] A careful evaluation of the transfer and retention of charge capabilities is critical in the early phases of the cell development. Typically, this is achieved by circuit simulation. HCspice DC Array device models are, for example, developed from measuring the DC Array device parameters, using them to characterize the storage and transient characteristics of the cell. These simulations are confirmed later when a product is available for testing. This approach has two inherent problems: 1) appropriate structures need to be designed for a direct probing of BS and DC characterization of the transfer device; and 2) the product test may come too late in the cell development, making it very difficult to (retroactively) optimize the cell design. It is desirable to test different cell designs, and readjust parameters of the cell, such as trench parameters, buried strap engineering, implants, oxide thickness, etc., at given voltages and temperatures.

[0006] One of the problems that exists in memory cell development during qualification activities for any trench based DRAM, is that it is not easy to stress the arrays in a real world memory environment. Most of the work that is done is at production level (burn-in, etc.). Burn-in is where, for example, a 250 megabit memory is provided and 250 million cells are exercised altogether. By doing so, certain circuit parameters, such as retention time and the like are tracked, particularly those that somehow are indirectly related to the actual cell operation. However, there is no previously known way to directly stress a cell with controlled inputs and sense the response of the single device cell in a real environment. Today, memory technologies develop the design on the production level, i.e., with millions of cells exercised by a process diagnostic monitor, by stressing them altogether. The array device features and sensitivities are thereby quantified indirectly. The present invention allows testing and stressing of the array device and cell to be performed directly rather than on a mass integration level.

[0007] Further, no method has been previously developed to directly measure the transfer and storage of charge in a realistic structure without a recurring product test. The prior art does not provide a circuit for directly measuring charge transfer/retention characteristics in DRAM one transistor cells. Neither does the prior art solve the problem on how to run key device DC reliability stresses on particular production cell structures and establish their impact on EOL (End of Life) projections.

[0008] The present invention provides a circuit that fundamentally probes a device in a network (directly stress) and senses the charge transfer characteristics. Eventually, each of the 250 million cells can be tested, as mentioned in the example above, but herein a direct link to one or a group of devices must be established. By selecting the bitline and wordline for each, one can run a product stress and investigate a single cell fail. It is now possible to electrically sense a single cell by focusing directly on the cell to stress it. Finally, one can also characterize the device of any cell in any environment to see if weak cells are present.

[0009] By exercising a DRAM cell device with a known time within which the cell stores a charge, the amount of charge stored, the length of time when most of the charge is retained and voltage is applied, one can generate and use this information by sending pulses to the cell in a way that one can characterize the charge transfer itself. This methodology can be used not only for testing charge transfer characteristics, but also for stressing the cell to perform lifetime wearout modeling.

[0010] The DRAM application described hereinafter is an example of how this process and circuit can be applied to characterize any charge transfer device in its production environment.

SUMMARY AND OBJECTS OF THE INVENTION

[0011] In a first aspect of the invention, there is provided a DRAM cell as part of an circuit whose basic elements are a MOSFET device connected in series with a capacitor used as a charge transfer device (FIG. 1C). MOSFET junction (3) (equivalent to BS) is connected to the capacitor and is not directly addressable. The charge exchange between capacitor (NC) and junction (1) takes place by modulating gate (2). It is of critical importance to characterize the charge retention and transfer of the capacitor and the MOSFET device, respectively. Since the junction (3) cannot be directly addressable this cannot be achieved by simple DC testing.

[0012] In a second aspect of the invention, there is provided a methodology as well as an on-chip circuit for characterizing the charge retention and transfer response of the basic circuit, as illustrated in FIG. 1C, using a realistic test sequence. Although this methodology can be used for this general structure, it will be described by using the vertical DRAM cell (shown in FIG. 1A).

[0013] Accordingly, it is an object of the invention to provide a new on-chip circuit and testing methodology that allow quantifying the transistor charge transfer and the NC charge storage capability of a DRAM cell in a realistic field environment.

[0014] It is another object of the invention to provide an on-chip circuit that imposes and senses a voltage in an individual DRAM storage capacitor.

[0015] It is still another object of the invention to provide a pulse test method to characterize an individual storage capacitor charge leakage rate while the wordline is at low and when a logic 1 is initially stored in the DRAM cell.

[0016] It is yet another object of the invention to provide a test method for quantifying the rate of charge transfer between the bitline and the storage capacitor in an individual DRAM cell.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Other features, aspects and advantages of this invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, when taken in conjunction with the accompanying drawings.

[0018]FIG. 1 illustrates a conventional vertical array DRAM cell.

[0019]FIG. 2 is a schematic of a typical DRAM cell circuit with tester loading used to illustrate the method of measuring the NC voltage by charge equalization between NC, BL, and the tester capacitance, according to the present invention.

[0020]FIG. 3 illustrates a schematic of the circuit used to monitor the charge retention and transfer to a DRAM cell, according to the invention.

[0021]FIG. 4 illustrates pulse stress/test parameter definitions.

[0022]FIG. 5 illustrates V(EQU) measurement after a (WL low) delay time.

[0023]FIG. 6 illustrates measuring the NC charge storage time at a given voltage and temperature.

[0024]FIG. 7 illustrates the measured V(EQU) as a function of T(WL Low), showing that the height of the pulse V(EQU) decreases when T(WL Low) increases.

[0025]FIG. 8 illustrates V(EQU) measurement after a WL delay time.

[0026]FIG. 9 shows the measured V(EQU) as a function of an applied V(WL).

[0027] FIGS. 10-13 illustrate pulse stress sequences applied to WL and BL.

[0028]FIG. 14 illustrates the expected shift of V(EQU) vs. V(WL ramp) characteristics.

[0029]FIG. 15 illustrates a stressing/testing procedure flowchart.

BEST MODE FOR CARRYING OUT THE INVENTION

[0030] The characterization of the NC charge storage and transistor charge transfer capabilities of a given DRAM cell are critical elements when optimizing its design. This evaluation cannot be carried out in an actual DRAM cell by constant voltage DC biasing means. In particular, a WL low condition (transfer device is in off channel conduction) does not allow direct DC access to BS.

[0031] Another challenge is that the testing device has much higher capacitance than the circuit (about 50 femtofarads in the current example) being tested. Thus, measuring a very small pulse coming out of a very low capacitance is difficult because by the time a measurement is performed, the signal is gone. A voltage amplifier local to the cell, i.e., on-chip, is thus needed. Typically, about 15 femtocoulombs are stored in the cell, hence, 1 volt on a 50 femtofarad cell, (considering handling hundreds of millivolts signal margin), results in a very small total voltage difference between two bitlines.

[0032] The on-chip circuit and testing methodology of the present invention quantify the transistor charge transfer and NC charge storage capability of a given DRAM cell in a realistic operation. This methodology can be extended to evaluate the aging of the cell transfer device due to MOSFET wearout mechanisms that can be activated during the charge transfer as well as storage in operation or burn-in conditions.

[0033] The application of the circuit and test methodology is not limited to any particular DRAM cell test and stress investigation. The method is advantageously used to stress and test any transfer-to-storage device even when all the terminals are readily accessible to the device. This is highly advantageous because a product-like stress and test can thus be provided.

[0034] The following observations highlight the benefits of the inventive apparatus and methodology. The Node Capacitor (NC) has the property of retaining stored charge for a time (Ts.c) during which the NC voltage is kept almost constant when the cell is not addressed (WL low). In the illustrative reference cell (NMOSFET as transfer device), when a logic 1 is written, an NC positive charge is stored when the NC/BS junction is reverse biased. Leakage mechanisms, such as the BS junction leakage, BS GIDL (Gate Induced Drain Leakage), or tunneling through the trench oxide, are activated by BS to PW as well as by the Node to BP voltage. All these mechanisms reduce Ts.c. By applying selected voltage pulses to BL and WL during period T (T<Ts.c), it is possible to set the BS/NC and BL voltages independently. If WL is kept low (the gate is off) during time Ts.c., BS remains mostly at voltage (V (BS)) while BL is independently biased. The BS voltage V(BS) was set previously by transferring charge from BL (apply V(BL)) to NC and by turning on the transfer device (WL high). For V(BL)=V(WL)=Vdd, the voltage at NC is V(BS)=Vdd−Vth, where Vth is the threshold voltage of the transfer device.

Charge Equalization Between NC, BL, and Tester Capacitance During NC Voltage Measurement

[0035] Assuming that the load capacitance due to the testing apparatus is C (tester), it can be proven that measuring V(NC) translates into a charge equalization between node (C (NC)), BL (C (BL)) and the tester (C (tester)) capacitance (see FIG. 2). Assuming that C(BL)<<C(NC) and C(tester)>C(NC), the measured Voltage V(EQU) relates to the voltage stored in NC (V(NC)) before the measurement by way of the following Formula 1:

V(EQU)=C(NC)×V(NC)/(C(NC)+C(BL)+C(tester))(C(NC)/C(tester)×V(NC))

[0036] If C(tester)>>C(NC), C(BL)<<C(NC) then V(EQU)<<V(NC).

[0037] It follows that:

[0038] 1) V(EQU) is proportional to V(NC), and the proportionality constant depends on C(BL), C(NC), and C(tester). The rate of change of V(NC) is estimated by measuring V(EQU) as a function of time.

[0039] 2) V(EQU) value is very small if C(tester)>>C(NC). Typical trench node capacitance is on the order of 40-50 fF, while C(tester) are on the order of pF. With C(tester)>>C(NC), the measured voltage (V(EQU)) may be lower than the tester noise and, as a result, is not measurable. Minimizing C(tester) relative to C(NC) and amplifying the V(EQU) signal allows to measure V(EQU) proportional to V(NC).

Independently Using the BL as a Vehicle to Apply and Sense Voltage on the NC (V(NC)=V(BS)).

[0040] The DRAM cell (or any structure as shown in FIG. 1C) can be considered a two terminal (WL and BL terminals) device structure. Since the WL is used to activate the charge transfer between BL and NC by the transfer device, BL is the only terminal to be used to apply and sense a voltage to NC. Therefore, there is provided an on-chip circuit that allows a user to impose and sense a voltage in NC as well as evaluate the transfer device characteristics in a realistic operational environment.

[0041]FIG. 3 shows the main features of a DRAM cell. This circuit has three main components:

[0042] 1) an on-chip voltage amplifier (A);

[0043] 2) a DRAM array (B) wherein only one cell is directly addressed by modulating a WL (1) and BL (3); and

[0044] 3) a SET BL SENSE logic (C).

[0045] The circuit includes three passgates and an inverter that allows, by selectively activating the passgates, to open and close WL and BL to transfer charge. The voltage amplifier is needed to amplify the signal out from the cell to the tester. The voltage amp does not change the shape of the pulse (it scales linearly), but it provides enough signal amplification so that it can be measured. There is no sense amp in the present embodiment which includes two circuits connected to the cell, and which allows testing to be performed. In a typical sense amp in a DRAM environment, the sense amp looks at the reference BL and the actual BL signals using a bistable circuit (which amplifies the signal by outputting a logic 1 when the voltage reaches a certain threshold).

[0046] The invention further provides a set of circuits coupled to the cell where the charge transfer (Vt) is directly sensed in a particular cell, which is sensed (tested) at the bitline.

[0047] A multiplexer (not shown) can be advantageously used together with the circuit of FIG. 3 to step through many cells, one at a time. A Set BL Sense Logic circuit and voltage amplifier circuit are needed for each tested cell. (Note: they do not need to be part of the memory cell, i.e., the BL sense and voltage amplifies can be placed on the chip, but external to the memory area). A variation thereof uses the circuit as a design device monitor/optimization tool, to be nested within every 20 to 30 memory cells for testing charge transfer characteristics. The circuit can be built on-chip to track the characteristics of the device and be used as an inline monitor.

[0048] The DRAM cell to be tested and stressed is part of a DRAM array is designed such that C(BL)<<C(NC). This can be accomplished by ensuring that it is the only cell contacted by WL (1) and BL (3) busses associated therewith. Thus, no other cell in the array is contacted by its WL and BL to ascertain that C(BL)<<C(NC) and that the V(EQU) reduction due to C(BL) is minimized. In addition, by having array cells connected to the same WL and BL, all the cells will be tested concurrently. This prevents having detailed information on a single cell Nesting of the testable cell is needed to ensure that the cell under investigation is part of a product like environment.

[0049] SET BL SENSE circuit consists of three passgates PG1, PG2, PG3 and an inverter I1. This circuit has two main functions:

[0050] a) to isolate the DRAM cell from the testing apparatus when voltage is applied to NC at BL FORCE node (3). This is achieved by setting SET-BL SENSE LOGIC Low at node (2). At the same time, PG1 allows setting a voltmeter at Set BL Sense Low; and

[0051] b) to measure the voltage stored in NC by charge equalization by setting SET-BL SENSE High at node (2). The passgates and inverter devices are designed to minimize their contribution to junction leakage and series resistance with respect to the transfer device.

[0052] The Set BL Sense Logic operates as follows. By activating Set BL Sense—sending the pulse (FIG. 3) to node (2), and by applying a pulse (WL force) on WL, charge is transferred to the cell capacitor. There is one node that is used for forcing and sensing, namely, BL out. The pass-gates with an inverter are arranged so that when one is forcing, one is not sensing, and vice versa. When node (2) is at high, PG3 turns to low (through the inverter) as does PG1 (PG2 switches to high). Then, the tester senses the voltage because the path from the cell through PG2 is open. When node (2) switches to low, PG3 opens and PG2 is off, the path from node (3) to the cell is open such that one can force node (3). The on-chip voltage amp remains on and does not require to be open or closed. Thus, it does not interfere with testing because it is totally disconnected by PG2 being off during test. Such an on-chip voltage amplifier is well know in the art and will not be further discussed herein.

[0053] The on-chip voltage amplifier is connected in series to BL sense circuit to amplify the Node Capacitor Voltage V(EQU) signal. The voltage amplifier should have a sufficiently high gain to allow measuring a reasonable voltage. During test/stress operations, the BL Force Voltage is set constant at node (3). During testing Set BL Sense as well as WL, voltages are pulsed respectively at nodes (2) and (1). The voltage at NC is monitored by measuring V(EQU) at node (4). When stressed, Set BL Force Voltage is low, so that the cell under stress is isolated from the testing equipment.

[0054] The action of forcing and sensing a voltage on NC is not restricted by the use of the inventive circuit. The invention extends to other possible circuit designs that satisfy the above required NC voltage forcing and sensing functions.

[0055] Using the proposed on-chip circuit allows to quantify Ts.c (TEST 1) and the transistor cell charge transfer capabilities, when T(WL Low)<<Ts.c (TEST2). This is done, for instance, for the DRAM array described in FIG. 3, and can be easily extended to an equivalent charge transfer MOSFET in series with a storage capacitor circuit.

[0056] With reference to FIG. 4, some definitions for the applied BL and WL pulsed stress/test as well as the induced BS pulse parameters are provided. When the transfer device is on, the BS and BL voltages are equalized. The equalization takes place by transfer of charge between BS and BL. The BS and BL voltages can be independently set when the transfer device is off (T(WL Low)<<Ts.c.).

Test 1 V(EQU) Measurement After “WL Low” Delay and Corresponding Ts.c Estimate

[0057] When a logic 1 is written into the DRAM cell, positive charge is stored on NC. When WL is set low (channel in accumulation), charge can leak out into the well. The rate of NC charge retention depends on the leakage mechanisms that are activated at the applied BS voltage and temperature. In order to optimize the WL and BL pulse waveforms required for testing/stressing the DRAM cell, it is important to characterize the charge leakage rate when a logic 1 is stored in the cell while WL is low. In particular, the time constant Ts.c during which the charge is stored in the NC is critical for keeping the BS and NC voltage almost constant.

[0058] The invention provides further a BL and WL pulse test methodology, based on the circuit described in FIG. 3, that allows characterizing the NC charge leakage rate while WL is low, when a logic 1 is initially stored in the cell.

[0059] With reference to FIG. 5, a constant voltage (V(BL)) is applied on BL Force node. A square pulse with period T is applied to SET-BL Sense circuit. During half-period (T1), the SET-BL Sense Voltage is at low, allowing a possible charge transfer from BL to NC without measurement. During T2, SET-BL SENSE voltage is set high so V(EQU) can be measured. According to Formula 1:

V(EQU)=V(NC)*C(NC)/C(tester).

[0060] For simplicity, the case T1=T2, T=T1+T2 will be treated. A WL square pulse of period T1=T2 is applied and delayed with respect to SET BL SENSE pulse by T4. During time T3, WL voltage is low and no charge transfer between NC and BL occurs. When WL is high and SET-BL Sense is low, charge transfer takes place from BL to NC. When WL and SET-BL SENSE are both at high, the charge is transferred from NC through BL to the tester, wherein V(EQU) is measured. During T3 (WL Low), the charge in NC can leak out. The value of measured V(EQU) depends on the voltage applied to NC when the charge is transferred to the node and the duration of T3. In particular, the longer T3, the lower V(EQU), when it is measured. Obviously, a maximum value of V(EQU) is obtained when T(WL Low)=0. By increasing T(WL Low), V(EQU) decreases.

[0061] With reference to FIGS. 6, 6A and 6B, there is shown the applied WL pulse with different WL low times T1, T2, T3, . . . , TN, and corresponding V(EQU) values H1, H2, H3, . . . , HN, when the same V(BL) is applied. FIG. 6C shows a possible dependence of V(EQU) on T(WL Low) for the same V(BL). The value of V(EQU) for the same T(WL Low) strongly depends on the NC charge leakage mechanisms activated by the voltage being applied to the BS reverse biased junction and by the temperature. Other mechanisms listed herein are expected to dominate at different bias conditions. During the time when V(EQU) is almost constant, Ts.c is expected to decrease with an increasing V(BS). FIG. 6C allows the estimate of Ts.c once a given V(EQU) decrease is given.

[0062]FIG. 7 shows the experimentally measured dependence of V(EQU) at three different T3 lengths. In the structure measured, the BL and WL applied voltage is 6V, and the measured V(EQU) is, as expected, in the range of 10-70 mV, when V(tester)>V(NC). The WL voltage is ramped up to 3 V. As expected, V(EQU) decreases with T(WL Low) delay time (FIG. 7B). The rate of V(EQU) is proportional to the rate of V(NC) change due to the NC leakage mechanisms.

Test 2 MOSFET Charge Transfer Measurement by Pulsed Test

[0063] Since it is not possible to independently bias BS when WL is low, typical DC MOSFET parameter characterization of the charge transfer transistor is very limited in a product type structure having a single BL, WL, and a non-accessible BS in WL low condition. Therefore, there is provided a “pulsed test” method that quantifies the rate of charge transfer between BL and BS (NC) in a product-type cell using the inventive circuit.

[0064] Two possible test conditions can be applied to characterize the charge transfer from BS to BL and from BL to BS, respectively.

Measurement of Charge Transfer from BL to BS

[0065] The steps for measuring the charge transfer between BL and BS will be explained with reference to FIG. 8. Measure Ts.c from Test 1 with V(BL) and temperature value of interest. Set the BL Voltage and the temperature of interest. Run test as in FIG. 8 where T(WL Low)=T3<<Ts.c. and WL ramp rate is low enough to resolve V(EQU) as a function of T(WL RAMP) rate. During T5, no charge transfer takes place since V(WL)<Vth. FIG. 8 shows the measured V(EQU) during T(WL RAMP).

[0066]FIG. 9A shows the measured V(EQU) versus the applied V(WL) during a slow WL ramp, as described in FIG. 7. The derivative of V(EQU) with respect to V(WL) as a function of WL ramp is proportional to current I=I(BL) measured during the charge transfer. $\frac{{V({EQU})}}{{V({WL})}} = {\frac{1}{R \times {C({Tester})}} \times 1}$

[0067] wherein C(Tester) is the tester capacitance, R is the WL ramp rate (V(WL))=R×t.

[0068]FIG. 9B shows the expected trend. An equivalent set of measurements is run to evaluate the BS to BL charge transfer.

[0069] Test 1 and test 2 methodologies in conjunction with the circuit illustrated in FIG. 3 can be implemented in production type array cells, where each of the cells can be individually probed. The estimate of Ts.c with V(EQU) can be correlated to the cell retention time. This implies that this technique allows to estimate the cell retention time without running any product type of stress. This pulse test methodology becomes critical in the development of the one transistor cell design.

Application of Proposed Circuit and Testing Methodology to Investigate Charge Transfer Device Wearout Mechanisms

[0070] Accelerated Constant Voltage (DC) stresses are typically used to investigate transistor wearout and their impact on its EOL lifetime. The possibility of investigating the transfer device wearout by DC stresses requires modifications to the DRAM cell in such a way that the BS junction can be directly accessed during the stress.

[0071] Contacting BS is not possible during operation. In addition, it is not recommended for the following reasons. Probing BS directly can modify the cell environment to the extent that the new structure will have a different level of sensitivity to the device damage. Probing BS directly introduces added process complexity, which increases the development and manufacturing cost.

[0072] The invention provides a pulsed transfer device aging approach that takes advantage of the condition that BS can be constant for a stress time Tstress<Ts.c at a given V(BS), while WL is low. The DRAM cell using an NMOSFET transfer device is shown for illustrative purposes only. This stress method can be applied to investigate the MOSFET degradation of any MOSFET with a Capacitor in series in a real world operation.

Description of Pulsed Hot Carrier (HC) Aging

[0073] With reference to the circuit illustrated in FIG. 3, an estimate Ts.c (stress) of the one transistor cell at V(BL) stress voltage and temperature of interest using test 1 is provided. Pulse stresses are applied to BL and WL in order to transfer a given voltage to NC, and to activate the given stress configuration of interest. For any of the pulse stress configurations, T(WL Low)<Ts.c. under the stated conditions, V(NC)=V(BS) remains unchanged during T(WL Low). Set BL Sense circuit is switched to low during stress to isolate the cell under stress from the testing circuit. A BL stress voltage is applied to BL force node (2) of FIG. 3. Additionally, the effect of the degradation experienced by the transfer device is estimated during the applied pulsed stress by monitoring its shift during charge transfer capability when applying test 2 under the stated conditions. Two possible “production like” transfer device aging modes are of interest: Aging during transfer of charge between BL and BS and aging having WL Low (Gate Off). Possible pulse stress configurations to investigate these two device aging mechanisms follow.

Transfer Device Aging During Transfer of Charge Between BL and BS

[0074] This type of aging phenomena is related to activating the MOSFET wearout mechanisms during the charge transfer. Channel conducting hot carriers are expected to degrade the device during the transients associated with the charge transfer. In this case, possible HC damage occurs at the junction with high-applied voltage. The following two pulsed stress configurations are used to investigate possible channel conducting HC damage in either or both BS and BL junctions.

[0075] 1) Vertical Device Aging During Transfer of Charge from (BL to BS) or (BS to BL)

[0076] With reference to FIG. 10, there is shown a pulse configuration that creates aging at the transfer NMOSFET due to charge transfer (electron) from BL to BS. The charge transfer takes place during transient T2. During this interval, WL is pulsed from low to high with BL low, while BS follows BL from high to low. For a very short time during the transient, a condition of HC injection takes place. A slow ramping pulse is applied during the period T1 with WL high to set BS high before HC transient. During T1, charge transfer from BS to BL occurs, but no HC damage takes place since WL is high (no peak Isx condition). Obviously, T(WL Low)<<Ts.c at stress. Similar stress with charge transfer from BS to BL takes place if V(BL) low and high are swapped relative to (BL to BS) transfer.

[0077] 2) Vertical Device Aging During Transfer of Charge Between BL and BS

[0078] With reference to FIG. 11, there is shown a pulse configuration that creates transfer device aging due to charge transfer between BS and BL. The charge transfer takes place during transient T1 (BS to BL) and T2 (BL to BS). For a very short period of time during the transient, a condition of HC injection takes place. With this type of pulsed stress, the device degradation due to HC damage in both BS and BL is experienced. Obviously, T(WL Low)<<Ts.c, at stress.

Charge Transfer Device Aging During WL Low

[0079] This type of aging phenomena relates to activating the MOSFET wearout during WL Low condition (when no charge transfer occurs). The channel non-conducting Hot Carrier mechanism is one of the mechanisms expected to degrade the device. The non-conducting HC damage occurs at the junction with high voltage. In addition, possible LITS (Leakage Induced Threshold Shift) is activated when both BS and WL are high and WL low. The following three pulsed stress configurations can be used to investigate possible WL low wearouts in either or both BS and BL junctions. In all stress conditions T(WL Low)<<Ts.c. For these stress configurations, Set BL Sense voltage is at low, isolating the sensing circuit (FIG. 3). In addition, BL low and high are respectively set by applying high and low at BL force Node (2).

[0080] 1) WL Low/(BS High/BL Low) or (BS Low/BL High)

[0081] With reference to FIG. 12, there is shown a pulse configuration that generates transfer device aging during WL low with BS high and BL low (during T1). During T1, (an off condition) conducting HC injection takes place (BS=drain). A stress configuration with BS low and BL high is achieved by swapping BL voltage relative to FIG. 11. Aging is the result of the non-conducting HC damage during the WL low regime.

[0082] 2) WL Low/BL and BS High

[0083] With reference to FIG. 13, there is shown a pulse configuration that creates transfer device aging due to WL, low with BL and BS high (during T1) simultaneously. During T1, a condition of LITS injection takes place. Aging is the result of the LITS HC damage during the WL low regime.

[0084] With reference to FIG. 14, during the stress run at the bias configurations given above, a different readout needs to be taken to measure the degradation of the charge transfer capability, as illustrated in FIG. 14(A) that shows the expected shift of V(EQU) vs. V(WL Ramp) of the pulsed stress during Test 2. The expected shift is shown in FIG. 14(B) depicting the expected shift of $\frac{\partial{V({EQU})}}{\partial{V({WL})}}{{VsV}\left( {{WL}\quad {ramp}} \right)}$

[0085] characteristics as a function of the pulse stressed during Test 2.

[0086]FIG. 15 illustrates a flow chart of the present test/stress method. By changing the height of WL and BL pulses, a different stress voltage is applied to each bias stress configuration. This feature allows a testing regime that establishes the voltage activation of a given wearout mechanism that the transfer device is sensitive to. Since the pulse of the stress is shorter than Ts.c, the stress in question takes place with BS and NC at a controlled applied voltage. No other mechanisms, different from those under investigation, are expected to be activated at the same time.

[0087] This approach allows lifetime projections for a device wearout. Other pulse shapes can be used to investigate other possible wearout mechanisms as well as to modulate the duty cycle as desired. The “pulsed stress” configurations described herein are provided by external pulse generators together with clocks or on-chip ring oscillators whose period is smaller than the retention time of the storage cell. These generators and clocks are well known articles of commerce and are not described herein. Similarly, the tester used for measuring voltages output from the DRAM cell are also well know articles of commerce and their specific use is not considered part of the invention described herein, thus, these devices are not described.

[0088] In further testing embodiments, random chips can be taken off an assembly line, each having the inventive circuit incorporated therein, and tested. A version of the invention can be fabricated in the chip kerf and run therefrom. A multiplexer can test a given range of cells. Strategically located cells can be selected for testing, and if they are all within a given tolerance it is known that one has a good chip. Dedicated package pins may be needed in these instances to activate the device.

[0089] Whereas the present invention has been described with respect to the foregoing embodiments, it is needless to say that various changes and modifications can be made without departing from the subject matter of the present invention, all of which fall within the scope and spirit of the appended claims. 

What is claimed is:
 1. An apparatus comprising: a substrate; a memory cell array formed in the substrate; and a circuit formed in the substrate electrically coupled to one memory cell of the memory cell array for transmitting test voltage signals to the one memory cell of the memory cell array and for transmitting from the one memory cell a scaled memory cell voltage level responsive to the test voltage signals.
 2. Apparatus of claim 1 wherein the circuit includes a bit line input node and a word line input node for receiving the test voltage signals, the test voltage signals including voltages transmitted on the bit line and on the word line, each coupled to the one memory cell.
 3. Apparatus of claim 2 wherein the one memory cell comprises a storage capacitor, the voltages transmitted on the bit line transfer charge to the storage capacitor, and wherein the scaled memory cell voltage level indicates a performance level of the one memory cell.
 4. Apparatus of claim 3 wherein the performance level includes a charge storage capability of the storage capacitor.
 5. Apparatus of claim 3 wherein the one memory cell further comprises a transfer device, and wherein the performance level includes a charge transfer performance of the transfer device.
 6. Apparatus of claim 1 wherein the circuit comprises a voltage amplifier for providing said scaled memory cell voltage level.
 7. Apparatus of claim 1 wherein the circuit comprises a bit line logic node and a logic circuit, wherein the logic circuit includes a pair of passgates both coupled to the bit line logic node for alternatively blocking the test voltage signals to the one memory cell of the memory cell array while permitting transmitting from the one memory cell the scaled memory cell voltage level and permitting the test voltage signals to the one memory cell of the memory cell array while blocking the transmitting from the one memory cell the scaled memory cell voltage level.
 8. Apparatus of claim 7 wherein the logic circuit further includes a first input node and a second input node, the first input node for receiving a selection signal that selects either of said alternatively blocking the test voltage signals while permitting transmitting from the one memory cell or permitting the test voltage signals while blocking the transmitting from the one memory cell, the second input node for receiving one of said test voltage signals for transmitting to the one memory cell of the memory cell array.
 9. A method for determining a charge retention performance of a memory cell, the method comprising the steps of: electrically coupling a constant voltage source having a voltage level to the memory cell; electrically connecting a first blocking device (PG3) and a second blocking device (WL transistor) between the constant voltage source and the memory cell; opening the first blocking device and the second blocking device including allowing charge transfer from the constant voltage source to charge the memory cell; closing the first and second blocking devices including preventing the charge transfer to the memory cell and determining a time duration during which the second blocking device is closed; opening the second blocking device while keeping closed the first blocking device including measuring a scaled voltage level of the memory cell; and calculating a charge retention performance level of the memory cell based on the voltage level of the voltage source, the measured scaled voltage level of the memory cell, and the time duration.
 10. The method of claim 9, wherein the calculating step includes the step of calculating a charge retention time. 